1. Field of the Invention
The present invention relates to a display device and a method for driving the same, more particularly relates to an active matrix type display device and a projection type display device of the point sequential drive system employing the so-called clock drive method for a horizontal drive circuit (horizontal scanner).
2. Description of the Related Art
Display devices, for example, active matrix type liquid crystal display devices using liquid crystal cells for display elements (electrooptic elements) of the pixels employ the point sequential drive system for the horizontal drive circuits (horizontal scanner portions).
FIG. 1 is a circuit diagram showing the configuration of an active matrix type liquid crystal display device employing the general point sequential drive system (refer to for example Japanese Patent Application No. 2001-109460).
This liquid crystal display device (LCD panel) 10 has, as shown in FIG. 1, a valid pixel portion (PXLP) 11, a vertical scanner (VSCN) 12, a horizontal scanner (HSCN) 13, a first clock generation circuit (GEN1: timing generator) 14, and a second clock generation circuit (GEN2) 15 as principal components. Note that, as shown in FIG. 2, the vertical scanner is sometimes arranged at not only one side portion of the pixel portion 11, but at both side portions, and is provided with a signal line precharge circuit (PRCG) 16.
The pixel portion 11 is comprised of a plurality of pixels PXL arrayed in a matrix of n number of rows and m number of columns. Here, for simplification of the figure, a case of a pixel array consisting of 4 rows and 4 columns will be shown as an example. Each of the pixels PXL arranged in the matrix is comprised of a pixel transistor constituted by a thin film transistor (TFT) 11, a liquid crystal cell LC with a pixel electrode connected to a drain electrode of this TFT 11, and a storage capacitor Cs with one electrode connected to the drain electrode of the TFT 11. With respect to each of these pixels PXL, has signal lines SGNL1 to SGNL4 are laid along the pixel array direction for every column and gate lines GTL1 to GTL4 are laid along the pixel array direction for every row. In each of the pixels PXL, a source electrode (or a drain electrode) of the TFT 11 is connected to each of the corresponding signal lines SGNL1 to SGNL4. The gate electrode of the TFT 11 is connected to each of the gate lines GTL1 to GTL4. The counter electrode of the liquid crystal cell LC and the other electrode of the storage capacitor Cs are connected to a Cs line CsL1 common to adjacent pixels. This Cs line CsL1 is given a predetermined DC voltage as a common voltage Vcom. In this pixel portion 11, first side ends of the gate lines GTL1 to GTL4 are connected to for example output ends of rows of the vertical scanner 12 arranged on the left side in the figure of the pixel portion 11.
The vertical scanner 12 performs processing for scanning pixels in the vertical direction (row direction) for every field period and sequentially selecting the pixels PXL connected to the gate lines GTL1 to GTL4 in units of rows. Namely, pixels of columns of the first row are selected when a scanning pulse SP1 is given from the vertical scanner 12 to the gate line GTL1, and pixels of the columns of the second row are selected when a scanning pulse SP2 is given to the gate line GTL2. Below, in the same way, scanning pulses SP3 and SP4 are sequentially given to the gate lines GTL 3 and GTL4.
For example an upper side in the figure of the pixel portion 11 is provided with the horizontal scanner 13. The horizontal scanner 13 performs processing for sequentially sampling input video signals VDO for every 1H (H is a horizontal scanning period) and writing them to the pixels PXL selected in units of rows by the vertical scanner 12. The horizontal scanner 13 employs a clock drive system as shown in FIG. 1 and has a register 131, a clock sampling switch group 132, a phase adjust circuit (PAC) group 133, and a sampling switch group 134.
The shift register 131 has four shift stages (S/R stages) 131-1 to 131-4 corresponding to the pixel columns (four columns in the present example) of the pixel portion 11 and performs a shift operation in synchronization with horizontal clocks HCK and HCKX having inverse phases to each other when the horizontal start pulse HST is given from the first clock generation circuit 14. Due to this, the shift stages 131-1 to 131-4 of the shift register 131 sequentially output shift pulses SFTP1 to SFTP4 having the same pulse width as the periods of the horizontal clocks HCK and HCKX.
The clock sampling switch group 132 has four switches 132-1 to 132-4 corresponding to the pixel columns of the pixel portion 11. First side ends of these switches 132-1 to 132-4 are alternately connected to the clock lines DKL1 and DKXL1 for sending the clocks DCKX and DCK of the second clock generation circuit 15. Namely, first side ends of the switches 132-1 and 132-3 are connected to the clock line DXL, and first side ends of the switches 132-2 and 132-4 are connected to the clock line DKL1. The switches 132-1 to 132-4 of the clock sampling switch group 132 are given the shift pulses SFTP1 to SFTP4 sequentially output from the shift stages 131-1 to 131-4 of the shift register 131. The switches 132-1 to 132-4 of the clock sampling switch group 132 respond to these shift pulses SFTP1 to SFTP4 and sequentially enter the ON state when the shift pulses SFTP1 to SFTP4 are given from the shift stages 131-1 to 131-4 of the shift register 131 and thereby alternately sample the second clocks DCKX and DCK having inverse phases to each other.
The phase adjust circuit group 133 has four phase adjust circuits 133-1 to 133-4 corresponding to the pixel columns of the pixel portion 11, adjust the phases of the second clocks DCKX and DCK sampled at the switches 132-1 to 132-4 of the clock sampling switch group 132, and then supply them to the corresponding sampling switches of the sampling switch group 134.
The sampling switch group 134 has four sampling switches 134-1 to 134-4 corresponding to the pixel columns of the pixel portion 11. First side ends of these sampling switches 134-1 to 134-4 are connected to a video line VDL1 for receiving as input the video signals VDO. The sampling switches 134-1 to 134-4 are given the clocks DCKX and DCK sampled by the switches 132-1 to 132-4 of the clock sampling switch group 132 and adjusted in phase at the phase adjust circuit group 133 as the sample-and-hold pulses SHP1 to SHP4. The sampling switches 134-1 to 134-4 of the sampling switch group 134 respond to the sample-and-hold pulses SHP1 to SHP4 and sequentially enter the ON state when the sample-and-hold pulses SHP1 to SHP4 are given and thereby sequentially sample the video signals VDO input through the video line VDL1 and supply them to the signal lines SGNL1 to SGNL4 of the pixel portion 11.
Further, the first clock generation circuit 14 generates a vertical start pulse VST for instructing the start of the vertical scan, vertical clocks VCK and VCKX having inverse phases to each other and acting as reference of the vertical scan, a horizontal start pulse HST for instructing the start of the horizontal scan, and horizontal clocks HCK and HCKX having inverse phases to each other and acting as reference of the horizontal scan, supplies the vertical start pulse VST and the vertical clocks VCK and VCKX to the vertical scanner 12, and supplies the horizontal clocks HCK and HCKX to the horizontal scanner 13 and the second clock generation circuit 15.
The second clock generation circuit 15 generates second clocks DCK and DCKX having inverse phases to each other which have the same period as the horizontal clocks (first clocks) HCK and HCKX generated at the first clock generation circuit 14 (T1=T2) and have a small duty ratio and supply them to the horizontal scanner 13. Here, the duty ratio means the ratio between a pulse width t and a pulse repetition period T in the pulse waveform. For example, as shown in FIGS. 3A to 3D, a duty ratio (t1/T1) of the horizontal clocks HCK and HCKX is 50%, and a duty ratio (t2/T2) of the clocks DCK and DCKX is smaller than this, that is, the pulse width t2 of the clocks DCK and DCKX is set narrower than the pulse width t1 of the horizontal clocks HCK and HCKX.
In the horizontal scanner 13, the shift pulses SFTP1 to SFTP4 sequentially output from the shift register 131 are not used as the sample-and-hold pulses. The clocks DCKX and DCK having inverse phases to each other are alternately sampled in synchronization with the shift pulses SFTP1 to SFTP4. These clocks DCKX and DCK are used as the sample-and-hold pulses SHP1 to SHP4 via the phase adjust circuit. By this, fluctuation of the sample-and-hold pulses SHP1 to SHP4 can be suppressed. As a result, ghosts caused by fluctuation of the sample-and-hold pulses SHP1 to SHP4 can be eliminated.
In addition, in the horizontal scanner 13, the horizontal clocks HCKX and HCK serving as the reference of the shift operation of the shift register 131 are not sampled and used as the sample-and-hold pulses. The clocks DCKX and DCK having the same period as the horizontal clocks HCKX and HCK and having a small duty ratio are separately generated. These clocks DCKX and DCK are sampled and used as the sample-and-hold pulses SHP1 to SHP4. Therefore, at the time of horizontal driving, complete nonoverlap sampling between sampling pulses can be realized, so generation of vertical stripes due to overlap sampling can be suppressed.
Here, for example, as shown in FIG. 4, an explanation will be given of the operation when writing video signals VDO at the corresponding pixels at the adjacent N-th stage and N+1-th stage in relation to FIGS. 5A to 5D. In this case, for example, when the video signal VDO, a drive signal DRVP-N of the N-th stage signal line SGNL-N, and a drive pulse DRVP-N+1 of the N+1-th stage signal line SGNL-N+1 have the timing relationships as shown in FIGS. 5A to 5C, ideally, a white signal is written into the N-th stage, and a black signal is written into the N+1-th stage, whereby an image without a ghost as shown in FIG. 5D is obtained.
In an LCD using TFTs, however, generally a change occurs in the characteristics of the transistors due to panel aging. Due to this change of characteristics, a pulse delay occurs in each transistor. Finally, the sample-and-hold pulse SHP drifts with respect to its initial state. Due to this drift, the optimum sample-and-hold position with respect to a ghost ends up shifting. With the sample-and-hold position setting at the time of the initial shipment as it is, the video signal of the adjacent stage ends up being sampled and held and a ghost is generated. Specifically, as shown in FIGS. 6A to 6C., the drive signal DRVP-N of the N-th stage signal line SGNL-N and the drive pulse DRVP-N+1 of the N+1-th stage signal line SGNL-N+l are delayed as indicated by a solid line after aging from the initial state indicated by a broken line. As a result, as shown in FIG. 6D, the black signal is written at the N-th stage, and a ghost GST is generated.
In order to prevent the generation of a ghost due to this drift, the measure of providing a monitor circuit (dummy scanner), outputting the output of the sampling switches thereof to the outside of the panel, monitoring the change of the phase from the initial state of the output by an external IC, and feeding back the amount of change of the phase to the clock of the panel input has become the general practice (refer to for example Japanese Unexamined Patent Publication (Kokai) No. 11-119746 and Japanese Unexamined Patent Publication (Kokai) No. 2000-298459).
FIG. 7 is a block diagram of an example of the configuration of a conventional liquid crystal display provided with a monitor circuit 17. FIG. 8 is a circuit diagram of a concrete example of the configuration of the monitor circuit 17 of FIG. 7 and part of the peripheral horizontal scanner 13.
The monitor circuit 17 of FIG. 8 is provided adjacent to the first stage of the horizontal scanner 13, that is, the stage to which the horizontal start pulse HST is input at first to start the shift operation. The monitor circuit 17 is ideally configured in the same way as the configuration of each stage of the horizontal scanner 13 for making the amounts of delay of the output pulses of the stages of the horizontal scanner 13 uniform. The monitor circuit 17 of FIG. 8 has a shift stage (S/R) stage 171 for receiving as input the horizontal start pulse HST and outputting a shift pulse SFTP17, a switch 172 for sampling the second clock DCKX by the shift pulse SFTP17 by the shift stage 171, a phase adjust circuit 173 for generating a sample-and-hold pulse SHP17 comprised of two signals taking complementary levels by adjusting the phase of the clock DCLX sampled by the switch 171, and a sampling switch 174 controlled in connection between the first terminal and the second terminal by the sample-and-hold pulse SHP17 by the phase adjust circuit 173.
The sampling switch 174 of the monitor circuit 17 is grounded at the first terminal and is connected to one end of the monitor line MNTL1 at the other end. The other end of the monitor line MNTL1 is connected to a feedback IC 18 of the outside of the LCD panel. The monitor line MNTL1 is pulled up at the outside of the panel. The external feedback IC 18 monitors the change of phase from the initial state from the timing when the sampling switch 173 becomes conductive and the monitor line MNTL1 shifts to the ground level and feeds back the amount of the change of the phase to the clock of the panel input. Note that the example of FIG. 8 is configured so that the horizontal clocks HCKX, HCK, etc. are generated by the external feedback IC 18.
Summarizing the problems of the invention, the active matrix type liquid crystal display device employing the point sequential drive system explained above is used as for example the display panel of a projection type liquid crystal display device (liquid crystal projector), that is, a LCD panel. In the case of color, three LCD panels are arranged corresponding to the three primary colors R (red), G (green), and B (blue). In this case, due to the relationships of the optical systems and the optical paths, in one liquid crystal display panel, it is necessary to invert from the other liquid crystal display panels and perform an inverse scan at the horizontal scanner. For this reason, the LCD panels are configured so as to have not only the function of scanning from for example the left side in the figure of FIG. 1, but also the function of scanning from the right side in the figure, that is, an inverse scan, in accordance with the application.
In a circuit provided with one conventional monitor circuit (dummy scanner), however, a horizontal scanner in which the phase of the clock is inverted by the left/right inversion has the following disadvantages since generally the number of the shift registers provided in the horizontal scanner 13 is even.
As shown in FIGS. 9A to 9K, when the scan is performed from left to right, for example, as shown in FIG. 9B, when assigning the notations <1>, <2>, and <3> to the pulses of the horizontal clock HCK, at the second timing <2> of the horizontal clock HCK and the timing of the second clock DCKX, the sample-and-hold pulse SHP1 of the first stage of the horizontal scanner 13 and the sample-and-hold pulse SHP17 of the monitor circuit 17 are generated at substantially the same timing and the image is display without problem.
As opposed to this, as shown in FIGS. 10A to 10K, when scanning from right to left, for example, as shown in FIG. 10B, when assigning the notations <1>, <2>, and <3> to the pulses of the horizontal clock HCK, at the first timing <1> of the horizontal clock HCK and the timing of the second clock DCKX, the sample-and-hold pulse SHP17 of the monitor circuit 17 is generated. SHP1 is generated at the timing <2> and the timing of the first clock DCK. Namely, in this case, the phase of the sample-and-hold pulse SHP17 for feedback was changed by the amount of one pulse by the left/right inversion, and correct feedback could not be carried out. In such a case, the image ends up being deviated by half and an image cannot be displayed with a high precision.